1. Field of the Invention
The present invention relates to a method for forming extension regions of each transistor in a semiconductor device that has a trench-type transistor and a planar-type transistor on a semiconductor substrate.
Priority is claimed on Japanese Patent Application No. 2007-85852, filed Mar. 28, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
For example, in a peripheral circuit transistor in a dynamic random access memory (DRAM), there are cases that require an N-channel MOS (NMOS) transistor with a high breakdown voltage compared to an ordinary NMOS transistor in some circuits. In this case, forming extension regions of a cell transistor and a high breakdown voltage NMOS transistor in the same photolithography step is one of the common methods.
However, in an N-region formation method for the case of adopting a trench-type transistor as the cell transistor, shifting of the registration positions of the trench and the gate pattern occurs. Therefore, it is preferred to form the extension regions by forming a gate material film and implanting ions from above the gate material film instead of forming the extension regions by the self-alignment method with respect to the gate edge. In that case, there is the advantage of being able to implant ions to the channel region of a trench-type transistor in the same photolithography step.
However, in the case of employing this method, it is impossible to form the extension regions of the aforementioned trench-type cell transistor and the high breakdown voltage NMOS transistor in the same photolithography step. Accordingly, it is necessary to provide a separate photolithography step for forming the extension region of the high breakdown voltage NMOS transistor, which leads to the problem of a cost increase.
The above situation will be described in reference to FIG. 3 to FIG. 5. Note that for the purpose of simplification, each single transistor in a trench-type cell transistor region, a high breakdown voltage NMOS transistor region, and an ordinary NMOS region that does not withstand a high voltage is illustrated as being adjoined, while a P-channel MOS (PMOS) region that is generally considered to exist is not illustrated. Also, since an upper insulating film, contact, and upper wiring and the like are formed by a general approach, the explanation is given without illustrating them for the purposes of simplification.
Element isolation regions 102, 103, 104, 105 are formed on a semiconductor substrate 101 as shown in FIG. 3, and each element is separately insulated. Here, from the left are shown a trench-type cell transistor region 106, a high breakdown voltage NMOS region 107, and an ordinary NMOS region 108 that does not withstand a high voltage. Next, a trench portion 113 for constituting the trench-type transistor is formed in the trench-type cell transistor region 106 using photolithography and dry etching technology so as to be sandwiched by the element isolation regions 102, 103.
Then, a gate insulating film 110 is formed by a general oxidation method on the surface of the semiconductor substrate 101 including the interior of the trench portion 113. Moreover, a gate material layer 111 is formed by the chemical vapor deposition (CVD) film forming method or the like on the gate insulating film 110. The gate material layer 111 is filled in the trench portion 113 via the gate insulating film 110.
From this state, after covering a region excluding the trench-type cell transistor region 106 with a photoresist film 117 as shown in FIG. 3, ions are implanted from above the substrate in the trench-type cell transistor region 106 as shown by the arrows A. Thereby, an N-type diffusion layer 118 is formed on both side portions of the trench portion 113 in the region between the element isolation regions 102, 103.
Next, the gate material layer 111 is patterned into the target shape using photolithography technology after removing the photoresist film 117 as shown in FIG. 4. That is, a gate electrode 120 is formed in the trench-type cell transistor region 106, a gate electrode 121 is formed in the high breakdown voltage NMOS region 107, and a gate electrode 122 is formed in the ordinary NMOS region 108. Next, the trench-type cell transistor region 106 and the high breakdown voltage NMOS region 107 are covered by a photoresist film 123, and ion injection is performed from above the substrate into the ordinary NMOS region 108 as shown by the arrows B. Thereby, an N− diffusion layer 125 is formed on the surface portion of the semiconductor substrate 101 on both sides of the gate electrode 122, and an ordinary breakdown voltage type NMOS transistor portion 126 is formed. Note that when forming the N− diffusion layer 125, generally a P-type diffusion layer region 125a is often formed by Halo (Pocket) implantation.
Next, after removing the photoresist film 123 as shown in FIG. 5, the trench-type cell transistor region 106 and the ordinary NMOS region 108 on the substrate are covered by a photoresist film 127. Next, ion implantation is performed from above the substrate as shown by the arrows C, and N− diffusion layers 129 are formed. In this manner, a high breakdown voltage NMOS transistor portion 130 of the high breakdown voltage NMOS region 107 is formed.
Thereafter, although not illustrated, a sidewall is formed on the gate side walls, and N+ diffusion layers are formed on the source/drain of the NMOS regions other than the trench-type cell transistor.
According to the steps shown in FIG. 3 to FIG. 5, the extension regions of the trench-type cell transistor region 106 and the high breakdown voltage NMOS region 107 cannot be formed in the same step. Accordingly, a photolithography step is separately required to form the extension regions of the high breakdown voltage NMOS region 107, that is, the N− diffusion layers 129, as shown in FIG. 5, which leads to an increase in the manufacturing cost.
Japanese Unexamined Patent Application, First Publication, (JP-A) No. 2004-281746 discloses a method that can reduce the number of steps in manufacturing a CMOS transistor structure that is provided with an NMOS transistor and a PMOS transistor. This method is used for forming a first and second semiconductor device by forming a first and second semiconductor thin film on a substrate and injecting an impurity in at least the first semiconductor thin film. That is, in this method, a metal film for forming an electrode is formed on the first and second semiconductor thin films, and an impurity injection mask is formed by patterning that covers an electrode of a first semiconductor element and the semiconductor thin film of the second semiconductor element. After injecting a first conductive type impurity in the first semiconductor thin film, an electrode of a second semiconductor element is formed by again patterning an impurity injection mask that covers the second semiconductor thin film. Then, a second conductive type impurity is injected in the first and second semiconductor thin films in low concentration with this electrode used as a mask.
Also, with the object of avoiding a drop in production yield due to junction leakage current, Japanese Unexamined Patent Application, First Publication, (JP-A) No. 2000-332634 discloses performing ion implantation via a photoresist layer in an N-type MOSFET (NMOSFET) region in order to form a lightly doped drain (LDD) region of the NMOSFET region. Specifically, ion implantation is performed simultaneously to a peripheral region of an element isolation layer of an NMOSFET region of a static random access memory (SRAM) circuit, and an auxiliary implantation region is formed. Consequently, a source/drain diffusion layer can be thickened in the vicinity of the element isolation layer.
Furthermore, Japanese Unexamined Patent Application, First Publication, (JP-A) No. H11-17024 discloses a method of manufacturing a semiconductor device having an NMOS transistor having an N-type gate electrode, and a PMOS transistor having a P-type gate electrode on the same substrate. This method consists of implanting impurity ions in each region to be removed by an etching process in a gate electrode film formed on a semiconductor substrate via a gate insulating film, so that the impurity compositions of the regions are equal or nearly equal, and then removing regions to be removed by etching to form gate electrodes of a predetermined pattern.
In the steps shown in FIG. 3 to FIG. 5 described above, the step of implanting ions in the trench-type transistor that is provided in the trench-type cell transistor region 106, the step of implanting ions in the high breakdown voltage transistor provided in the high breakdown voltage NMOS region 107, and the step of implanting ions in the transistor provided in the ordinary NMOS region are respectively performed by individual photolithography steps. For that reason, a photolithography step is separately required to provide a photoresist film for the step of implanting ions in the high breakdown voltage NMOS region compared to conventional methods, leading to the problem of a higher manufacturing cost due to the increased number of steps.
Also, even when applying the technology disclosed in the patent documents described above, no contribution is made to a simplification of the manufacturing procedures described based on the aforementioned FIG. 3 to FIG. 5.